An Inverted Coil represents the opposite result instruction of the conditions (contacts and/or function blocks) on the Ladder net before the Inverted Coil. An Inverted Coil instruction can be:
The result instruction can be to an external output device (for example: alarm bell) or to an internal system element (for example: SB 80 activate linearization).
During the system scan, the processor evaluates all of the program elements on the Ladder net before the Inverted Coil for power flow continuity.
If no power flow continuity exists in the net: the Inverted Coil address instruction is ON (logic 1).
If power flow continuity exists in the net: the Inverted Coil address is OFF (logic 0).